1. Field of the Invention
The present invention relates to a bandgap voltage reference circuit for generating a reference voltage.
2. Description of the Related Art
FIG. 3 illustrates a circuit diagram of a conventional bandgap voltage reference circuit. The conventional bandgap voltage reference circuit is constituted by PMOS transistors 311, 312, and 313, bipolar transistors 301, 302, and 303, resistors 106, 107, 108, 109, 110, 331, and 332, amplifiers 102 and 321, a power supply terminal 101, and a ground terminal 100.
The following describes connection. The amplifier 102 is configured such that an inverting input terminal is connected to a connecting point between an emitter of the bipolar transistor 301 and the resistor 107 and to the resistor 110, a noninverting input terminal is connected to a connecting point between the resistor 108 and the resistor 106 and to the resistor 109, and an output is connected to a gate of the PMOS transistor 311. Another end of the resistor 107 is connected to the resistor 332 and another end of the resistor 108. The bipolar transistor 301 is configured such that a base and a collector are connected to the ground terminal 100. The bipolar transistor 302 is configured such that an emitter is connected to another end of the resistor 106 and a base and a collector are connected to the ground terminal 100. The bipolar transistor 303 is configured such that an emitter is connected to another end of the resistor 109 and another end of the resistor 110 and a base and a collector are connected to the ground terminal 100. The PMOS transistor 311 is configured such that a drain is connected to another end of the resistor 332 and an inverting input terminal of the amplifier 321, and a source is connected to the power supply terminal 101. The amplifier 321 is configured such that a noninverting input terminal is connected to a drain of the PMOS transistor 313 and the resistor 331, and an output is connected to a gate of the PMOS transistor 312 and a gate of the PMOS transistor 313. The PMOS transistor 312 is configured such that a drain is connected to an emitter of the bipolar transistor 303, and a source is connected to the power supply terminal 101. A source terminal of the PMOS transistor 313 is connected to the power supply terminal 101. Another end of the resistor 331 is connected to the ground terminal 100.    [Non Patent Document 1] ISSCC 2010/SESSION 4/ANALOG TECHNIQUES/4.3 (FIG. 4.3.3)